The present invention relates generally to programmable logic devices (PLDs), and more particularly to reducing power consumption in such devices.
It should be noted that the term PLD as used herein is intended to cover the broad space of programmable logic. This includes devices commonly known as CPLDs (Complex Programmable Logic Devices) such as MAX 7000® from Altera Corporation of San Jose, Calif., FPGAs (Field Programmable Gate Arrays) such as Stratix® from Altera, or Structured ASICs (metal programmable logic) such as Hardcopy® from Altera.
Examples of known programmable logic devices are shown in Cliff et al. U.S. Pat. Nos. 5,909,126 and 5,963,049, which are hereby incorporated by reference herein in their entireties. PLDs typically include large numbers of regions of programmable logic and other operational resources such as memory, input/output circuits, etc., that are selectively interconnectable via programmable interconnection resources on the device. For example, each region of programmable logic on a PLD may be programmable to perform any of several relatively simple logic functions on several input signals applied to that region in order to produce one or more output signals indicative of the result of performing the selected logic function(s) on the input signals. The interconnection resources are programmable to convey voltage signals (ranging from a ground voltage VSS (e.g., a “LOW” voltage signal) to a source voltage VCC (e.g., a “HIGH” voltage signal) to, from, and between the logic regions in any of a wide variety of patterns or configurations. For example, the interconnection resources may be used to concatenate several logic regions so that much more complex logic tasks can be performed than any one logic region can perform.
It is typical to use a single conductor for each individual interconnection pathway or path segment in PLDs. Single or multiple MOS pass gates (controlled by programmable memory elements or circuits on the PLD) are used for selectively interconnecting each conductor to other conductors to provide various signal routings through the interconnection resources of the device.
The operation of a typical single-transistor pass gate may be succinctly illustrated by a description of an NMOS pass gate (analogous principles of operation, as understood by one skilled in the art, would apply for a PMOS pass gate). Depending on whether the potential difference between its gate terminal, VGATE, and its source terminal, VSOURCE, exceeds the threshold voltage, VT, an NMOS pass gate acts as an “open” or a “closed” switch. (As is well-known in the art, there is no physical difference between the “source” and “drain” terminals of a MOS device.) When VGATE−VSOURCE is less than VT, the NMOS pass gate is in the “cutoff” state, thereby acting as an “open” switch; when VGATE−VSOURCE is greater than VT, the NMOS pass gate is in the conduction state, thereby acting as a “closed” switch.
As is well-known in the art, VT is not a discrete value for a MOS transistor; it may be considered a range of values that is influenced by a variety of second-order effects, such as substrate bias and subthreshold conduction. However, in order to simplify the illustration of the principles of the present invention, VT will be discussed herein as if it is a discrete value rather than a range of values.
With the current trend in scaling down device geometries (e.g., 0.18 μm process down to 0.13 μm, 90 nm, 65 nm, or lower) and the consequent use of ever-lower operating voltages (e.g., supply voltages, bias voltages, etc.), which are nearing levels comparable to VT, the ability of transistor pass gate structures to function at relatively high speeds while at the same time minimizing leakage current is a difficult design hurdle to overcome.
Moreover, this trend of smaller device geometries and consequent use of lower operating voltages is creating a design tradeoff between speed (e.g., response time for the pass gate transistor to turn ON) and leakage current (e.g., the current that passes through the pass gate transistor when turned OFF) that was not previously experienced with larger device geometries and the consequent use of higher operating voltages. That is, if conventional design techniques are applied to smaller device geometries, high speed pass gate operation is accompanied with high leakage current, whereas low leakage current is accompanied with low speed pass gate operation. High leakage current is undesirable because it results in excess heat, power loss, and poorer performance.
Another problem associated with shrinking geometries is the consequent use of lower operating voltages. This lower operating voltage is typically a nominal voltage supplied to the device, and may be insufficient for certain circuitry, such as configurable memory cells (e.g., SRAM) within the device, to operate properly. For example, as the supply voltage decreases, the soft-error-rate increases because the critical charge needed to flip the cells (from one logic state to another) is reduced.
A large percentage of a device's power is consumed by the capacitive charging and discharging of the interconnection conductors. At lower operating voltages, the VT drop of NMOS pass gates becomes a more significant fraction or percentage of the operating voltage. This can lead to several problems in conventional PLD interconnection circuitry. For example, signaling slows down and the circuitry becomes increasingly susceptible to capacitive cross-talk between parallel conductors.
Accordingly, it would be desirable to provide improved techniques, systems, and methods for lowering the internal signaling power consumption of a programmable logic device.